Evaluating fault tolerance on asymmetric multicore systems‐on‐chip using iso‐metrics

نویسندگان
چکیده

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Evaluating Asymmetric Multicore Systems-on-Chip using Iso-Metrics

The end of Dennard scaling has pushed power consumption into a first order concern for current systems, on par with performance. As a result, near-threshold voltage computing (NTVC) has been proposed as a potential means to tackle the limited cooling capacity of CMOS technology. Hardware operating in NTV consumes significantly less power, at the cost of lower frequency, and thus reduced perform...

متن کامل

Evaluating the Fault Tolerance Capabilities of Embedded Systems via BDM

• Fault tolerant system System which is redundant to faults so that output is not affected • Why do we need fault tolerant systems? Vast increase in role of embedded systems in day to day applications, critical systems • How to verify the fault tolernace of embedded systems?

متن کامل

On Fault Tolerance Methods for Networks-on-Chip On Fault Tolerance Methods for Networks-on-Chip

Technology scaling has proceeded into dimensions in which the reliability of manufactured devices is becoming endangered. The reliability decrease is a consequence of physical limitations, relative increase of variations, and decreasing noise margins, among others. A promising solution for bringing the reliability of circuits back to a desired level is the use of design methods which introduce ...

متن کامل

Fault Tolerance on Star Graphs

A multiprocessor system consists of a set of processing units and each of them has its own local memory. The processing units in a multiprocessor system are linked in some topology. What we are interested in is a topology proposed by Akers et al. [2,3], called star graph. An n-dimensional star graph can be represented by S,, = (V,,, E,,), where V,, consists of n! nodes in which each node is ide...

متن کامل

Fault Tolerance Evaluation Using Two Software Based Fault Injection Methods

A silicon independent C-Based model of the TTP/C protocol was implemented within the EU-founded project FIT. The C-based model is integrated in the C-Sim simulation environment. The main objective of this work is to verify whether the simulation model of the TTP/C protocol behaves in the presence of faults in the same way as the existing hardware prototype implementation. Thus, the experimental...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: IET Computers & Digital Techniques

سال: 2016

ISSN: 1751-8601,1751-861X

DOI: 10.1049/iet-cdt.2015.0056